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The gated serial A and B inputs permit complete control over incoming data, a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock CLK pulse. A high-level input enables the other input, which then determines the state of the first flip-flop.

Data at the serial inputs can be changed while CLK is high or low, provided the minimum set-up time requirements are met. Clocking occurs on the low-to-high-level transition of CLK. FindIC uses cookies to provide you with the best website explerience.

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EN 10138-4 PDF




8-Bit Parallel-Out Serial Shift Registers


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