And the Uart0 can transmit and receive data fine; when change the code to use uart2, the uart2 only can transmit data, but lpc will reset and can't receive data when host transmit data to lpc; I had checked the code several times. I find the lpc can't go into the interrupt, but I can't deal with it. But It maybe a wrong operation in LPCx. I will test it tonight. In the end, it is important to always read through the documentation for the used chip and make sure that what you do matches the documentation and not just matches previous experiences with other chips.
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User manual. Document information. Philips Semiconductors. Revision history. LPC23xx User manual. Changes made to edition:. Contact information. All rights reserved. Chapter 1: Introductory information. Only when needed, a specific device name will be used to single out one of them. Single Flash se ctor or full chip erase in ms and bytes programming in 1 ms.
Can also be used as general purpose SRAM. These functions reside on an independent AHB bus. These reside on the APB bus. One is an alternate for the SPI port, sharing its interrupt and pins. Chapter 1: LPC Introductory information.
The second and third I 2 C interfaces are expansion I 2 Cs with standard port pins rather than special open drain I 2 C pins. Each Timer block has an external count input. The PWM has two external count inputs. Single 3.
Four external interrupt inputs. Processor wakeup from Power Down mode via any interrupt able to operate during Power Down mode includes external interrupts, RTC interrupt, and Ethernet wakeup interrupt. Two independent power domains allow fine tuning of power consumption based on needed features. Brownout detect with separate thresholds for interrupt and forced reset. On-chip Power On Reset. On-chip crystal oscillator with an operating range of 1 MHz to 24 MHz.
Boundary scan for simplified board testing. LPC only. Versatile pin function selections allow more possibilities for using on-chip peripheral functions. Ordering options. Table 1. Type number. SRAM kB. LPCFB Table 2. LPC ordering options.
Ext Bus. Local bus. Architectural overview. The microcontroller implements two AHB buses in order to allow the Ethernet block to operate without interference caused by other system activity. In addition, a bus bridge is provided that allows the secondary AHB to be a bus master on AHB1, allowing expansion of Ethernet buffer space into off-chip memory or unused space in memory residing on AHB1.
Lower speed peripheral functions are connected to the APB bus. APB peripherals are also allocated a 2 MB range of addresses, beginning at the 3. This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor core.
Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory.
On-Chip flash memory system. This memory may be used for both code and data storage. Programming of the Flash memory may be accomplished in several ways. It may be programmed In System via the serial port. The Flash is bits wide and includes pre-fetching and buffering techniques to allow it to operate at SRAM speeds. The write-back buffer always holds the last data sent by software to the SRAM. The data is only written to the SRAM when software does another write.
After a "warm" chip reset, the SRAM does not reflect the last write operation. Two identical writes to a loca tion guarantee that the data will be present after a Reset. Alternatively, a dummy write operation before entering idle or power-down mode will similarly guarantee that the last data written will be presen t after a subsequent Reset.
Block diagram. Fig 1. Fig 2. LPC block diagram. Chapter 2: LPC memory addressing. Memory map and peripheral addressing. ARM processors have a single 4 GB address space. The following table shows how this space is used on Philips embedded ARM devices.
Table 3. LPC memory usage. Address range. General use. Address range details and description. Flash Memory up to kB. Fast GPIO registers. On-Chip RAM. RAM up to 32 kB. Ethernet RAM 16 kB. Static memory bank 0, 64 KB. Static memory bank 1, 64 KB. APB Peripherals. System Control Block. AHB Peripherals. Ethernet Controller. USB Controller. Memory maps. The LPC incorporates several distinct memory regions, shown in the following figures.
Figure 2—3 shows the overall map of the entire address space from the user program viewpoint following reset. The interrupt vector area supports address remapping, which is described later in this section.
Chapter 2: LPC Memory map. Fig 3. Fig 4. LPC system memory map. Fig 5. Peripheral memory map. Figure 6 and Table 2—4 show different views of the peripheral address space. Each peripheral space is 16 kilo bytes in size. This allows simplifying the address decoding for each peripheral. All peripheral register addresses are word aligned to 32 bit boundaries regardless of their size. This eliminates the need for byte lane mapping hardware that would be required to allow byte 8 bit or half-word 16 bit accesses to occur at smaller boundaries.
An implication of this is that word and half-word registers must be accessed all at once. For example, it is not possible to read or write the upper byte of a word register separately.
NXP (founded by Philips) LPC2366
LPC2366 uart2 can't receive data